The present invention relates to a burn-in stress control circuit for a semiconductor memory device, and more particularly, to a control circuit that will limit the peak current generated in a semiconductor memory device while burn-in stress is being applied to the device.
During fabrication of a semiconductor memory device, the number of defects generated in a chip increases with the degree of integration of the chip. As the chip becomes more highly integrated, the size of each transistor on the chip is reduced. When the external supply voltage intended for the larger transistor is applied to the smaller transistor, stress associated with a strong electric field increases the failure rate of the transistor. Accordingly, in order to detect defects of the memory cells, and thereby ensure reliability of the chip, a burn-in stress is applied to the chip after fabrication of the chip. During the burn-in, a voltage higher than the external source voltage prescribed in the specification of the chip is applied to the chip for a long period of time at a high temperature, in order to detect a failed device when the chip is completed. By this method, the stress applied to each component or device of the chip increases, to detect initial failure.
FIG. 1 is a circuit diagram of a conventional DRAM semiconductor memory device. Referring to FIG. 1, the circuit includes: a plurality of word line drivers 11; word lines 15 connected to each of the word line drivers 11; a plurality of memory cells 13 connected to the word lines 15; and a row decoder 17 and a PX signal generator 19, both of which are connected to the word line drivers 11. Each of the word line drivers 11 is structurally the same--each comprises one PMOS transistor Q1 and two NMOS transistors Q2 and Q3. The sources of the PMOS transistors Q1 are connected to the PX signal generator 19 and the drains thereof are connected to the word lines 15. The drains of the NMOS transistors Q2 and Q3 are connected to the word lines 15, and their sources are connected to QUIET.sub.-- VSS. The gates of the PMOS transistors Q1 and the NMOS transistor Q2 are connected to the row decoder 17, and the gates of the NMOS transistors Q3 are connected to the PX signal generator 19.
FIG. 2 is a schematic of a conventional burn-in stress control circuit that includes first and second NMOS transistors 21 and 23 having their drains connected together. An inverter 25 has an input terminal connected to the gate of the first NMOS transistor 21 and an output terminal connected to the gate of the second NMOS transistor 23. A wafer burn-in enable signal PWBE is connected to the gate of the first NMOS transistor 21. A word line drive voltage Vpp is applied from the row decoder 17 to the source of the first NMOS transistor 21 and the source of the second NMOS transistors 23 is connected to a ground potential terminal Vss.
Referring to the circuit shown in FIG. 2, a method of applying the burn-in stress to a memory cell transistor Q4 of FIG. 1 is described as follows. Here, only the word line driver 11 having the PMOS transistor Q1, the first NMOS transistor Q2 and the second NMOS transistor Q3, and a device Q4 connected thereto will be described. In a state of standby before the burn-in stress is applied or a read/write operation occurs, both a word line enable signal output from the row decoder 17 and a normal mode voltage output from the PX signal generator 19 have a high logic level. Consequently, the PMOS transistor Q1 is deactivated, and the first and second NMOS transistors Q2 and Q3 are activated, and thus the word line is electrically connected to a QUIET.sub.-- VSS line.
When PWBE is a low logic signal, a fourth NMOS transistor 23 is activated, and thus the QUIET.sub.-- VSS line is grounded through Vss. Accordingly, the memory cell transistor Q4 is deactivated, and thus the burn-in stress is not applied to the memory cell transistor Q4.
Next, when the circuit is in a burn-in mode for applying the burn-in stress, the PWBE is enabled, by applying a high logic signal thereto. Then, the third NMOS transistor 21 is activated and the fourth NMOS transistor 23 is deactivated, and thus a burn-in stress boltage (Vpp-Vt) is applied to the QUIET.sub.-- VSS line. Here, Vt denotes threshold voltage of the third NMOS transistor 21. Since the first and second NMOS transistors Q2 and Q3 are activated, the burn-in stress voltage (Vpp-Vt) is transferred to the word lines 15. Accordingly, the memory cell transistor Q4 is activated by, and thus the burn-in stress is applied to the memory cell transistor Q4.
When the burn-in stress is completed after a predetermined period of time, PWBE is disabled, the third NMOS transistor 21 is deactivated, the fourth NMOS transistor 23 is activated, and thus the QUIET.sub.-- VSS line and the word line are both grounded through Vss, thereby stopping the application of the burn-in stress to the memory cell transistor Q4.
In order to reduce the noise generated in the QUIET.sub.-- VSS line, the resistance of the fourth NMOS transistor 23 is minimized by structurally enlarging its size. The third NMOS transistor 21 is also structurally enlarged, since the word line may come into contact with the bit line during the fabrication of the semiconductor, and when the PWBE is enabled, the QUIET.sub.-- VSS line is electrically connected to the bit line, and thus, the voltage level of the QUIET.sub.-- VSS line is reduced to (Vpp-Vt) or less.
When PWBE is changed to a low logic signal or a high logic signal, the voltage of each word line is changed to Vss or (Vpp-Vt). Here, since the third and fourth NMOS transistors 21 and 23 have a large structure, the peak currents thereof increase. Accordingly, the increased peak current causes an electro-migration phenomenon, which thereby causes a short of the QUIET.sub.-- VSS line.